Gate stability of GaN-Based HEMTs with P-Type Gate

status: publishe

The Role of Frequency and Duty Cycle on the Gate Reliability of p-GaN HEMTs

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers

Impact of the substrate and buffer design on the performance of GaN on Si power HEMTs

Abstract This paper presents an extensive analysis of the impact of substrate and buffer properties on the performance and breakdown voltage of E-mode power HEMTs. We investigated the impact of buffer thickness, substrate resistivity and substrate miscut angle, by characterizing several wafers by means of DC and pulsed measurement. The results demonstrate that: (i) the resistivity of the silicon substrate strongly impacts on the breakdown voltage and vertical leakage current. In fact, highly resistive substrates may partly deplete under high vertical bias, thus limiting the total potential drop on the epitaxial layers. As a consequence, the vertical I V plots show a "plateau", that limits the vertical leakage. (ii) the depletion of the substrate may worsen the dynamic performance of the devices, due to an enhancement of buffer trapping. (iii) Larger buffer thickness results in an increased robustness of the vertical stack, due to the thicker insulating region. (iv) the miscut angle (0°, 0.5°, and 1°) can significantly impact on both threshold voltage and the 2DEG density; devices with miscut substrate have higher current density. On the other hand, the dynamic on-resistance variation is comparable in the three cases

Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-Assisted C-V analysis. Under positive gate stress, small negative V th shifts (low stress) and a positive V thshifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-Trapping energy ≈2.95 eV. UV-Assisted CV measurements describe the distribution of states at the GaN/Al2O3 interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors

Exploration of Gate Trench Module for Vertical GaN devices

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported.Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020

Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices

Compact modeling of charge trapping processes in GaN transistors is of fundamental importance for advanced circuit design. The goal of this article is to propose a methodology for modeling the dynamic characteristics of GaN power HEMTs in the realistic case where trapping/detrapping kinetics are described by stretched exponentials, contrary to ideal pure exponentials, thus significantly improving the state of the art. The analysis is based on: 1) an accurate methodology for describing stretched-exponential transients and extracting the related parameters and 2) a novel compact modeling approach, where the stretched exponential behavior is reproduced via multiple RC networks, whose parameters are specifically tuned based on the results of 1). The developed compact model is then used to simulate the transient performance of the HEMT devices as a function of duty cycle and frequency, thus providing insight on the impact of traps during the realistic switching operatio

The 2018 GaN Power Electronics Roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here

The 2018 GaN power electronics roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here